For sake of clarity of the disclosure the following remarks are done. In this text the term complementary binary logic refers to a logic circuitry comprising a set of logic elements that correspond either to semiconductor logic elements or to complementary semiconductor logic elements each of them having an input and an output. During a steady state in the complementary binary logic circuitry                the potential at an input or at an output can have only two different values which are referred to as logic potentials, and        there are no conductive paths between the nodes in the set of semiconductor logic elements that are at different potentials enabling thus low steady state power consumption.        
In addition, it is only possible in complementary binary logic to establish a network of logic elements having the outputs of logic elements connected to the inputs of other logic elements and wherein the inputs/outputs of logic elements are biased only at a two different potentials that are the same throughout the network.
It is important to note that the term logic separates a semiconductor logic element and logic circuitries comprising semiconductor logic elements from analog regulation elements/circuitries. It should be also noted that in this text the terms binary logic, complementary logic, and logic are utilized generally in a context referring to the complementary binary logic since no other logic types are examined in this text. Furthermore, in this text the CMOS logic is referred to as traditional Complementary Conductor Insulator Semiconductor (CCIS) logic due to broader and more accurate scope. In a similar fashion a MOSFET is referred to as Conductor Insulator Semiconductor Field Effect Transistor (CISFET). The traditional CCIS logic is based on two opposite type enhancement mode CISFETs.
FIG. 2 illustrate a schematic layout of the two opposite type enhancement mode CISFET and FIG. 1 illustrates a schematic cross-section of the two opposite type enhancement mode CISFET along the dashed line 271 of FIG. 2. The backslash lines in FIGS. 1 and 2 refer to first conductivity type and the slash lines refer to second conductivity type. The two different conductivity types refer to p and n type but which way they are arranged is not relevant.
The CISFET on the left hand side comprises a first conductivity type source doping 111 corresponding to source, a first conductivity type drain doping 113 corresponding to drain and output, an external gate 125 corresponding to gate and output, a layer of gate insulator material 161 surrounding the external gate (except at the location of the gate contact), a second conductivity type back-gate doping 147, and a second conductivity type contact doping 117 to the back-gate doping 147. The CISFET on the right hand side comprises a second conductivity type source doping 112 corresponding to source, a second conductivity type drain doping 114 corresponding to drain and output, an external gate 126 corresponding to gate and input, a layer of gate insulator material 161 surrounding the external gate (except at the location of the gate contact), a first conductivity type back-gate doping 148, and a first conductivity type contact doping 118 to the back-gate doping 148. The both CISFETs and the contact dopings are surrounded by an insulator trench 162. Beneath the CISFETs there is a semiconductor substrate 100 of either conductivity type.
The back-gate doping can be connected to a separate node referred to as auxiliary gate node and the potential on the auxiliary gate node can be used to adjust the threshold voltage of the corresponding CISFET. In case the back-gate doping of the CISFET is of the same conductivity type as the semiconductor substrate then the auxiliary gate node is common to all CISFETs of this type. When the back-gate doping of the CISFET is of the opposite conductivity type than the substrate then this type CISFETs have individual auxiliary gate nodes. It is possible to have individual auxiliary gate nodes for both type CISFETs by incorporating underneath CISFETs an insulator layer and by incorporating deep enough trenches that reach to this insulator layer but this would increase the cost. Another option is to provide a suitable well doping of the opposite doping type than the substrate that can be used for isolating the substrate from the same conductivity type back-gate doping. The back-gate doping can be connected also to the source of the corresponding CISFET but in this case the ability to adjust the threshold voltage is lost. The second type CISFET on the right comprising the source, input, and output corresponds to a traditional semiconductor logic element comprising a source, input, and output. Similarly, the first type CISFET on the left comprising the source, input, and output corresponds to a traditional complementary semiconductor logic element having afore described source, input, and output. The traditional semiconductor logic element and the traditional complementary semiconductor logic element enable the realization of traditional complementary binary logic being capable of performing logic operations. Consequently, the said the two opposite type CISFETs enable the realization of traditional CCIS logic being capable of performing logic operations.
In the traditional CCIS logic it is a common arrangement that in a set of traditional semiconductor logic elements and of traditional complementary semiconductor logic elements the second conductivity type source of the traditional semiconductor logic element is connected to a first logic potential, that the first conductivity type source in the traditional complementary semiconductor logic element is connected to a second logic potential, that the gate 126 acts as the input and the drain 114 as the output of the traditional semiconductor logic element, that the gate 125 acts as the input and the drain 113 as the output of the traditional complementary semiconductor logic element, and that the inputs and outputs of the traditional semiconductor and complementary semiconductor logic elements can be during steady state only at the first logic potential or at the second logic potential. Furthermore, in the traditional semiconductor logic element a channel connecting the source and the drain is                nonconductive when the source and input are at first logic potential, and        conductive when the source is at first logic potential and the input is at second logic potential. Similarly in a traditional complementary semiconductor logic element a channel connecting the source and the drain is        nonconductive when the source and input are at second logic potential, and        conductive when the source is at second logic potential and the input is at first logic potential. In the traditional CCIS logic afore said common arrangement is utilized in order to perform logic operations. An important operational feature of afore said arrangement in the traditional CCIS logic is that when the input is at the same logic potential than the source in the traditional semiconductor logic element or in the traditional complementary semiconductor logic element then the output can be at either logic potential (at first logic potential or at second logic potential), i.e., the input has no control over the output. On the other hand when the input and the source are at different logic potentials then the output is set to the same logic potential as the source, i.e., the input determines the logic potential on the output.        
A great and unique benefit of the traditional CCIS logic is that it consumes only very little power. This is due to the fact there are no conductive current paths between two nodes that are at different potentials in the part of the traditional CCIS logic circuitry that is in steady state, i.e., during steady state the power consumption is due to leakage only which is not the case in any other present semiconductor logic arrangement. A big benefit of the traditional CCIS logic is also that the corresponding traditional semiconductor logic elements and traditional complementary semiconductor logic elements consume only very little area and thus a lot of circuitry can be packed into a small area resulting in low cost. Another big benefit of the traditional CCIS logic is that in the conductive stage the channel corresponds to an inversion layer of mobile charge carriers meaning that a lot of charge can be packed into the channel resulting in fast operation. Beside the low power consumption, low cost, and fast operation the traditional CCIS logic has, however, also numerous problems.
A problem in the traditional CCIS logic is that only a thin gate insulator layer separates at least two logic nodes from each others the logic lines being the input gate line as well as drain and/or source line. In case in the insulator layer between the two logic nodes there is a defect that is generated either during manufacturing or during operation then the defect can result in the formation of a permanent conductive path between at least two logic lines corrupting simultaneously at least two logic lines. The problem that a defect can corrupt simultaneously at least two logic lines means that the damage is more difficult to isolate, that countermeasures against defects are more difficult to design, and that complete device breakage is more likely resulted in.
Another problem related to the traditional CCIS logic is that in order to establish an inversion layer a high quality insulator semiconductor interface is required underneath the external gate forming the gate. Such a high quality insulator semiconductor interface is present only in some semiconductor materials like in silicon (Si), silicon germanium (SiGe), and silicon carbide (SiC). Thus there are many semiconductor materials wherein traditional CCIS logic cannot be incorporated. This leads for example to the problem in semiconductor sensors based on other than afore said materials that a silicon readout chip has to be bonded (e.g. by utilizing face to face flip chip bonding) to the sensor chip. The bonding results in yield issues due to bad bonds or due to wafer breakage. An inherent problem is also that the silicon readout chip and the sensor chip have typically considerably different thermal expansion coefficients which may lead to device breakage particularly if the sensor has to be cooled e.g. with thermoelectric coolers.
Yet another problem related to the traditional CCIS logic is that very accurate control of the insulator semiconductor interface quality, of the amount of insulator charge, of the k value of the insulator, and of the insulator thickness is required in order to achieve a desired level of control over the threshold voltage, i.e., in order to achieve properly functioning traditional CCIS logic a high quality Conductor Insulator Semiconductor (CIS) stack corresponding to the external gate is required. For example if the difference in the amount of insulator charge is large across the wafer bad yield may be resulted in. A problem is also that gate insulator charge (e.g. positive oxide charge in silicon) is generated by radiation damage in the gate insulator layer causing threshold voltage shifts reducing likely the lifetime of the device.
A substantial problem is also that the temperature that is required for the manufacturing of a high quality CIS stack corresponding to the external gate exceeds typically considerably the temperature that is required for the annealing of the ion implantation induced lattice damage as well as for the activation of the implanted impurity atoms. This increases considerably the thermal budget for doped regions that are implanted before the manufacturing of the CIS stack (corresponding to the external gate acting as the gate). Thus the design complexity is increased, transistor scaling to smaller dimensions is impeded, and performance is impaired. Even if in some semiconductor material the formation of a good quality CIS stack would be possible it may be that the temperature for the formation of the CIS stack is so high that the tendency for the dopant atoms to diffuse essentially prevents the formation of functional CISFETs.
An additional problem in traditional CCIS logic is also that the CIS stack sets a limit for the maximum operational temperature of the chip. Without the CIS stack the chips could be operational at much higher temperatures which would reduce the need for cooling and which would increase the operational range and field of chips. Yet another problem in state of the art small line width CCIS logic is power consumption due to leakage from source to drain passing through the channel and due to leakage through the gate insulator.
Finally, a problem in mixed mode chips comprising digital logic and low noise analog electronics is that low voltage (e.g. 1.8 V) traditional CCIS logic for low power small foot print digital logic part as well as relatively high voltage (e.g. 3.3 or 5 V) traditional CCIS logic for the low noise analog part are required. This necessitates the manufacturing of two CIS stacks with two different insulator thicknesses increasing considerably the thermal budget of the manufacturing and thus complicating the manufacturing and design of mixed mode chips leading to higher cost. It should be also noted that in mixed mode chips based on traditional CCIS logic the amount of binary logic potential level pairs (typically two like e.g. 1.8 V and 5 V) is very limited and that it would be highly desired to have more logic level pairs available.
In the publication “Complementary logic with 60 nm poly gate JFET for 0.5 V operation”, Kapoor A. K. et al, Electronics Letters, Volume 46, Issue 11, Pages 783-784, May 27, 2010, traditional Complementary Junction Field Effect Transistor (CJFET) logic has been realized. In the traditional CJFET logic the enhancement mode CISFETs of traditional CCIS logic have been replaced with enhancement mode JFETs. The benefit of the traditional CJFET logic is that problems of traditional CCIS logic related to the gate insulator and to the interface beneath the gate insulator have been removed. Another advantage is that very low operation voltage range (i.e. 0.5 V) is required only. A problem with the traditional CJFET logic is, however, that when the enhancement JFETs (corresponding to traditional semiconductor logic elements) are conductive the doped region acting as the gate is forward biased with respect to the source resulting in leakage current running between the gate and the source. Another point, which increases also considerably the leakage current is that in the nonconductive stage the channel of the enhancement mode JFET is not truly nonconductive. Due to the higher leakage current the steady state power consumption of the traditional CJFET logic is much higher than in traditional CCIS logic. Yet another problem with traditional CJFET logic is that the operation voltage is fixed, i.e. one cannot realize higher operation voltages that would be required in mixed mode chips.
It would be also possible to replace enhancement mode JFETs in traditional CJFET logic with similar type enhancement mode Metal Semiconductor Field Effect Transistors (MESFETs), which are later on referred to as Conductor Semiconductor Field Effect Transistors (CSFETs, corresponding also to traditional semiconductor logic elements). In this manner traditional Complementary MESFET (CMESFET) logic or traditional Complementary CSFET (CCSFET) logic could be realized but it would be prone to the same problems as the traditional CJFET logic.
As can be seen from above the traditional solutions, as identified above in an exemplified manner, have many problems. Thus, there is need to develop solutions, which at least partly mitigate the one or more problems pointed out in the context of the traditional solutions.